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Edoardo Bonizzoni, Ph.D.


 


 

 

 

 

 


         

Edoardo Bonizzoni was born in Pavia, Italy, in 1977. He received the Laurea degree (summa cum laude) in Electronic Engineering from the University of Pavia, Italy, in 2002. From the same University, he received in 2006 the Ph.D. degree in Electronic, Computer, and Electrical engineering.

In 2002 he joined the Integrated Microsystems Laboratory of the University of Pavia as a Ph.D. candidate. During his Ph.D., he worked on development, design and testing of non-volatile memories with particular regard to phase-change memories. From 2006 his research interests are mainly focused on the design and testing of DC-DC and A/D converters. In this period he worked on single-inductor multiple-output DC-DC buck regulator solutions and on both Nyquist-rate and oversampled A/D converters. Recently, his research focuses on the design of high precision amplifiers and ultra-low voltage voltage reference circuits as well. Presently, he is an Assistant Professor at the Department of Electrical, Computer, and Biomedical Engineering of the University of Pavia.

Dr. Bonizzoni is co-recipient of the IEEE/IEEJ Analog VLSI Workshop(AVLSIWS) 2010 best paper award, of the IEEE European Solid-State Circuits Conference (ESSCIRC) 2007 best paper award and of the IEEE/IEEJ Analog VLSI Workshop (AVLSIWS) 2007 best paper award.

Since 2012, he is an Associate Editor of the IEEE Transactions on Circuits and Systems - Part. II. Dr. Bonizzoni has been nominated Best TCAS-II Associate Editors for the 2012-2013 term. Since 2013 he is a TPC member of the IEEE Conference on Ph.D. Research in Microelectronics and Electronics (PRIME). He is IEEE member from 2006.


Pubblications

Book Chapters

* M. Belloni, E. Bonizzoni, and F. Maloberti, “Single-Inductor Multiple-Output DC-DC Converters"; Book chapter of "Analog Circuit Design, High Speed Clock and Data Recovery, High Performance Amplifiers and Power Management", edited by M. Steyaert, A.H.M. Van Roermund, and H. Casier, Springer Science+Businness Media 2008, pp. 233-253, ISBN 978-1-4020-8943-5.

Thesis

* E. Bonizzoni, “Phase-change memories”, Ph.D. Thesis, University of Pavia, 2006.
* E. Bonizzoni, “Model and algorithm for design of maximum-efficiency Dickson charge pumps”, Laurea Degree Thesis, University of Pavia, 2002.

Journal Papers

* A. Pena Perez, E. Bonizzoni, and F. Maloberti, "A 88 dB DR, 84 dB SNDR Very Low-Power Single Op-Amp Third-Order Sigma-Delta Modulator", IEEE Journal of Solid-State Circuits, vol. 47, pp. 2107-2118, Sept. 2012.
* O.Belotti, E. Bonizzoni, and F. Maloberti, "Exact Design of Continuous-Time Sigma-Delta Modulators with Multiple Feedback DACs", Analog Integrated Circuits and Signal Processing, DOI 10.1007/s10470-012-9866-z, vol. 73, pp. 255-264, 2012.
* N. Kumar Y.B., E. Bonizzoni, A. Patra, and F. Maloberti, "Two-path double delay line based band-pass quadrature ΣΔ modulator," IET Electronics Letters, vol. 47, pp. 1316–1317, Nov. 2011.
* H. Caracciolo,E. Bonizzoni, P. Malcovati, and F. Maloberti, "70-MHz IF 10-MHz bandwidth bandpass sigma-delta modulator for WCDMA applications," Analog Integrated Circuits and Signal Processing, On Line First October 2011, DOI 10.1007/s10470-011-9795-2, vol. 71, no. 3, pp. 411-419, June 2012.
* A. Agnes, E. Bonizzoni, and F. Maloberti, "High-resolution multi-bit second-order incremental converter with 1.5-mV residual offset and 94-dB SFDR," Analog Integrated Circuits and Signal Processing, On line first, DOI 10.1007/s10470-011-9752-0, vol. 72, pp. 531-539, Sept. 2012..
* M. Belloni, E. Bonizzoni, A. Fornasari, and F. Maloberti, “A Micropower Chopper-CDS Operational Amplifier”, IEEE Journal of Solid-State Circuits, vol. 45, n. 12, pp. 2521-2529, Dec. 2010.
* E. Bonizzoni, A. Pena Perez, F. Maloberti, and M.A. Garcia-Andrade, “Two Op-Amps Third-Order Sigma-Delta Modulator with 61-dB SNDR, 6-MHz Bandwidth and 6-mW Power Consumption”, Analog Integrated Circuits and Signal Processing, DOI: 10.1007/s10470-010-9538-9, vol. 66, pp. 381-388, 2011.
* A. Agnes, E. Bonizzoni, P. Malcovati, and F. Maloberti, "An Ultra-Low Power Successive Approximation A/D Converter with Time-Domain Comparator", Analog Integrated Circuits and Signal Processing, vol. 64, pp. 183-190, August 2010.
* M. Belloni, E. Bonizzoni, P. Malcovati, and F. Maloberti, " A High Efficiency 4-Output Single Inductor DC-DC Buck Converter with Self Boosted Snubber ", Analog Integrated Circuits and Signal Processing, DOI: 10.1007/s10470-010-9570-9, vol. 67, pp. 169-177, 2011.
* E. Bonizzoni, F. Borghetti, P. Malcovati, and F. Maloberti, “A 200-mA, 93% Peak Power Efficiency, Single-Inductor, Dual-Output DC-DC Buck Converter”, Analog Integrated Circuits and Signal Processing, vol. 62, no. 2, pp. 121-129.
* I. Galdi, E. Bonizzoni, P. Malcovati, G. Manganaro, and F. Maloberti, “40-MHz IF 1-MHz Bandwidth Two-Path Band-Pass ΣΔ Modulator with 72-dB DR Consuming 16 mW”, IEEE Journal of Solid-State Circuits, vol. 43, no. 7, pp. 1648-1656, July 2008.
* F. Bedeschi, C. Boffino, E. Bonizzoni, C. Resta, and G. Torelli, “Staircase Down SET Programming Approach for Phase-Change Memories”, ELSEVIR Microelectronics Journal, 38, pp. 1064-1069, 2007.
* F. Bedeschi, R. Bez, C. Boffino, E. Bonizzoni, E. Buda, G. Casagrande, L. Costa, M. Ferraro, R.Gastaldi, O. Khouri, F. Ottogalli, F. Pellizzer, A. Pirovano, C. Resta, G. Torelli, and M. Tosi, “4 Mbit MOSFET-selected µtrench phase-change memory experimental chip”, IEEE Journal of Solid-State Circuits, vol. 40, no. 7, pp. 1557-1565, July 2005.

Conference Papers

* Y. Liu, E. Bonizzoni, A. D'Amato, and F. Maloberti, "A 105-dB SNDR, 10 kSps Multi-Level Second-Order Incremental Converter with Smart-DEM Consuming 280 uW and 3.3-V Supply", Proc. of IEEE European Solid-State Circuits Conference (ESSCIRC), pp. 371-374, Sept. 2013.
* H. Heidari, U. Gatti, E. Bonizzoni, and F. Maloberti, "Low-Noise Low-Offset Current-Mode Hall Sensor", Proc. of IEEE Conference on Ph.D. Research in Microelectronics and Electronics (PRIME), pp. 325-328, June 2013.
* O. Belotti, E. Bonizzoni, F. Maloberti, "Design of a Third-Order ΣΔ Modulator with Minimum Op-Amps Output Swing", Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), pp. 821-824, May 2013.
* Y. Liu, E. Bonizzoni, F. Maloberti, "High-Order Multi-Bit Incremental Converter with Smart-DEM Algorithm", Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), pp. 157-160, May 2013.
* Y.B. Nithin Kumar, H. Caracciolo, E. Bonizzoni, A. Patra, F. Maloberti, "A 1.96-mW, 2.6-MHz Bandwidth Discrete Time Quadrature Band-Pass ΣΔ Modulator", Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1998-2001, May 2013.
* Y.B. Nithin Kumar, E. Bonizzoni, A. Patra, F. Maloberti, "Two-Path Quadrature Cascaded Band-Pass Sigma-Delta Modulators", 26th International Conference on VLSI Design, VLSI Design 2013, pp. 221-226, Jan. 2013.
* E. Bonizzoni, A. Pena Perez, H. Caracciolo, D. Stoppa, and F. Maloberti, "An Incremental ADC Sensor Interface with Input Switch-Less Integrator Featuring 220-nVrms Resolution with +/-30mV Input Range", Proc. of IEEE European Solid-State Circuits Conference (ESSCIRC), pp. 389-392, Sept. 2012.
* N. Kumar Y.B., E. Bonizzoni, A. Patra, and F. Maloberti, "Interference Rejection in Delay Line Based Quadrature Band-Pass ΣΔ Modulators", Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), pp. 3005-3008, May 2012.
* O. Belotti, E. Bonizzoni, and F. Maloberti, "A 1-V 1.1-MHz BW Digitally Assisted Multi-Bit Multi-Rate Hybrid CT ΣΔ with 78-dB SFDR", Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), pp. 289-292, May 2012.
* N. Kumar Y.B., E. Bonizzoni, A. Patra, and F. Maloberti, "Two-path delay line based quadrature band- pass ΣΔ modulator", Proceedings of IEEE/IEEJ Analog VLSI Workshop (AWVLSI), pp. 65–69, Nov. 2011.
* Y. Liu, E. Bonizzoni, and F. Maloberti, "Digital assisted high-order multi-bit analog to digital ramp converters," Proceedings of IEEE European Conference on Circuit Theory and Design (ECCTD), pp. 593–596, Aug. 2011.
* O. Belotti, E. Bonizzoni, and F. Maloberti, "Mono-rate and multi-rate hybrid continuous-time ΣΔ
modulators with SC feedback DAC," Proceedings of IEEE International Symposium on Signals, Circuits
and Systems (ISSCS)
, June 2011.
* A. Pena Perez, E. Bonizzoni, and F.Maloberti, “A Low-Power Third-Order Sigma-Delta Modulator Using a Single Operational Amplifier”, Proc. of IEEE International Symposium on Circuit and Systems (ISCAS), pp. 1371-1374, May 2011.
* A. Pena Perez, E. Bonizzoni, and F.Maloberti, “A 84dB SNDR 100kHz Bandwidth Low-Power Single Op-Amp Third-Order Sigma-Delta Modulator Consuming 140µW”, IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, 477-478, Feb. 2011.
* V.R. Gonzalez-Diaz, E. Bonizzoni, and F.Maloberti, “Pseudorandom Sequence Generation for Mismatch Analog Compensation of ADCs”, Proc. of IEEE International Conference on Electronics, Circuits, and Systems (ICECS), pp. 118-121, Dec. 2010.
* A. Pena Perez, O. Belotti, E. Bonizzoni, and F.Maloberti, “A Two Op-Amps Third-Order ΣΔ Modulator with Complex Conjugate NTF Zeros”, Proc. of IEEE International Conference on Electronics, Circuits, and Systems (ICECS), pp. 689-692, Dec. 2010.
* A. Agnes, E. Bonizzoni, A. D'Amato, I. Galdi, F. Maloberti, "High-Resolution Multi-Bit Incremental Converter with 1.5-µV Residual Offset and 94-dB SFDR", Proc. of IEEE/IEEJ International Analog VLSI Workshop (AVLSIWS), pp. 103-106, Sept. 2010. (Best paper award)
* M. Belloni, E. Bonizzoni, F. Maloberti, A. Fornasari: "Low-Power Ripple-Free Chopper Amplifier with Correlated Double Sampling De-Chopping", Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), pp. 765-768, May 2010.
* H. Caracciolo, E. Bonizzoni, P. Malcovati, F. Maloberti: "Design of a 70-MHz IF 10-MHz Bandwidth Bandpass ΣΔ Modulator for WCDMA Applications", Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), pp. 2406-2409, May 2010.
* H. Caracciolo, E. Bonizzoni, F. Maloberti, G.S. La Rue: "Digitally Assisted Multi-Bit ΣΔ Modulator", Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), pp. 3993-3996, May 2010.
* M. Belloni, E. Bonizzoni, A. Fornasari, and F. Maloberti, “A Micropower Chopper-Correlated Double-Sampling Amplifier with 2µV Standard Deviation Offset and 37nV/sqrt(Hz) Input Noise Density”, IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 76-77, Feb. 2010.
* F. Maloberti, E. Bonizzoni, and A. Surano, “Time Variant Digital Sigma-Delta Modulator for Fractional-N Frequency Synthesizers”, Proc. of IEEE Radio-Frequency Integration Technology (RFIT), pp. 111-114, Dec. 2009.
* M. Belloni, E. Bonizzoni, and F. Maloberti, “High Efficiency DC-DC Buck Converter with 60/120-MHz Switching Frequency and 1-A Output Current”, Proc. of IEEE European Solid-State Circuits Conference (ESSCIRC), pp. 452-455, Sept. 2009.
* S. Noli, A. Perez, E. Bonizzoni, and F. Maloberti, “Sigma-Delta Time Interleaved Current Steering DAC with Dynamic Elemnts Matching”, Proc. of IEEE Midwest Symposium on Circuits and Systems (MWSCAS), pp. 407-410, Aug. 2009.
* A. Surano, E. Bonizzoni, and F. Maloberti, “On-Chip Sine Wave Frequency Multiplier for 40-GHz Signal Generator”, Proc. of IEEE Ph.D. Research in Microelectronics and Electronics (PRIME), pp. 284-287, July 2009.
* A. Perez, N. Kumar Y.B., E. Bonizzoni, and F. Maloberti, “Slew-Rate and Gain Enhancement in Two-Stage Operational Amplifiers”, Proc. of International Symposium on Circuit and Systems (ISCAS), pp. 2485-2488, May 2009.
* E. Bonizzoni, A. Perez, F. Maloberti, and M. Garcia-Andrade, “Third-Order ΣΔ Modulator with 61-dB SNR and 6-MHz Bandwidth Consuming 6 mW”, Proc. of IEEE European Solid-State Circuits Conference (ESSCIRC, pp. 218-221, Sept. 2008.
* E. Bonizzoni, A. Perez, and F. Maloberti, “Non-Conventional ΣΔ Architectures for Very Low-Power and Medium Resolution Applications”, Proc. of IEEE/IEEJ International Analog VLSI Workshop (AVLSIWS), pp. 135-139, July 2008.
* M. Belloni, E. Bonizzoni, and F. Maloberti, “On the Design of Single-Inductor Double-Output DC-DC Buck, Boost, Buck-Boost Converters”, Proc. of IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp. 626-629, Sept. 2008.
* F. Erario, A. Agnes, E. Bonizzoni, and F. Maloberti, “Design of an Ultra-Low Power Time Interleaved SAR Converter”, Proc. of IEEE Ph.D. Research in Microelectronics and Electronics (PRIME), pp. 245-248, June 2008.
* M. Belloni, E. Bonizzoni, and F. Maloberti, “A Voltage-to-Pulse Converter for Very High Frequency DC-DC Converters”, Proc. of IEEE International Symposium on Power Electronics, Electrical Drives, Automation and Motion (SPEEDAM), pp. 789-791, June 2008.
* M. Belloni, E. Bonizzoni, and F. Maloberti, “On the Design of Single-Inductor Multiple-Output DC-DC Buck Converters”, Proc. of International Symposium on Circuit and Systems (ISCAS), pp. 3049-3052, May 2008.
* A. Agnes, E. Bonizzoni, and F. Maloberti, “Design of an Ultra-Low Power SA-ADC with Medium/High Resolution and Speed”, Proc. of International Symposium on Circuit and Systems (ISCAS), pp. 1-4, May 2008.
* H. Caracciolo, I. Galdi, E. Bonizzoni, and F. Maloberti, “Band-Pass Sigma-Delta Architectures with Single and Two Parallel Paths”, Proc. of International Symposium on Circuit and Systems (ISCAS), pp. 1656-1659, May 2008.
* M. Belloni, E. Bonizzoni, E. Kiseliovas, P. Malcovati, F. Maloberti, T. Peltola, and T. Teppo, “A 1.2A Output Current Single-Inductor 4-Output DC-DC Buck Converter with Self-Boosted Switch Drivers”, IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 444-626, Feb. 2008.
* A. Agnes, E. Bonizzoni, P. Malcovati, and F. Maloberti, “A 9.4 ENoB, 1V, 3.8mW, 100 kS/s SAR-ADC with Time-Domain Comparator”, IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 246-610, Feb. 2008.
* H. Caracciolo, E. Bonizzoni, and F. Maloberti, “Quasi-Second Order ΣΔ Modulator Based on Phase-Integration”, Proc. of IEEE/IEEJ International Analog VLSI Workshop (AVLSIWS), pp. 19-22, Nov. 2007. (Best paper award)
* I. Galdi, E. Bonizzoni, F. Maloberti, G. Manganaro, and P. Malcovati, “Two-path band-pass ΣΔ modulator with 40-MHz IF 72-dB DR at 1-MHz bandwidth consuming 16 mW”, Proc. of IEEE European Solid-State Circuits Conference (ESSCIRC), pp. 248 – 251, Sept. 2007. (Best paper award)
* A. Lombardi, P. Malcovati, A. Basto, E. Bonizzoni, and F. Maloberti, “An optimized two stage low power sinc3 filter for ΣΔ modulators”, Proc. of IEEE Ph.D. Research in Microelectronics and Electronics (PRIME), pp. 81-84, July 2007.
* I. Galdi, E. Bonizzoni, and F. Maloberti, “Design of a current-mode 6-bit 100 MS/s flash A/D converter with 0.75 pJ/conv-lev FoM”, Proc. of IEEE Ph.D. Research in Microelectronics and Electronics (PRIME), pp. 69-72, July 2007.
* A. Lombardi, E. Bonizzoni, P. Malcovati and F. Maloberti, “A low power sinc3 filter for ΣΔ modulators”, Proc. of IEEE International Symposium on Circuit and Systems (ISCAS), pp. 4008-4011, May 2007.
* E. Bonizzoni, F. Borghetti, P. Malcovati, F. Maloberti, and B. Niessen, “A 200mA 93% peak efficiency single-inductor dual-output DC-DC buck converter”, IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 526-527, Feb. 2007.
* F. Bedeschi, C. Boffino, E. Bonizzoni, C. Resta, G. Torelli, and D. Zella, “Set-sweep programming pulse for phase-change memories”, Proc. of IEEE International Symposium on Circuit and Systems (ISCAS), pp. 967-970, May 2006.
* F. Bedeschi, C. Boffino, E. Bonizzoni, O. Khouri, G. Pollaccia, C. Resta, and G. Torelli, “A low-ripple voltage tripler”, Proc. of IEEE International Symposium on Circuit and Systems (ISCAS), pp. 2753-2756, May 2006.
* F. Bedeschi, E. Bonizzoni, G. Casagrande, R. Gastaldi, C. Resta, G. Torelli, and D. Zella, “SET and RESET pulse characterization in BJT-selected phase-change memories”, Proc. of IEEE International Symposium on Circuit and Systems (ISCAS), pp. 1270-1273, May 2005.
* R. Arona, E. Bonizzoni, F. Maloberti, and G. Torelli, “Heap charge pump optimisation by a tapered architecture”, Proc. of IEEE International Symposium on Circuit and Systems (ISCAS), pp. 1903-1906, May 2005.
* F. Bedeschi, C. Boffino, E. Bonizzoni, O. Khouri, C. Resta, and G. Torelli, “Fast-recovery CMOS voltage regulator for large capacitive loads”, Proc. of IEEE International Conference on Signal and Electronic Systems (ICSES), pp. 349-352, Sep. 2004.
* F. Bedeschi, C. Boffino, E. Bonizzoni, O. Khouri, C. Resta, and G. Torelli, “Bit-line biasing technique for phase-change memories”, Proc. of IEEE International Conference on Signal and Electronic Systems (ICSES), pp. 229-232, Sep. 2004.
* F. Bedeschi, R. Bez, C. Boffino, E. Bonizzoni, E. Buda, G. Casagrande, L. Costa, M. Ferraro, R.Gastaldi, O. Khouri, F. Ottogalli, F. Pellizzer, A. Pirovano, C. Resta, G. Torelli, and M. Tosi, “4 Mbit MOSFET-selected phase-change memory experimental chip”, Proc. of IEEE European Solid-State Circuits Conference (ESSCIRC), pp. 207-210, Sep. 2004.
* F. Bedeschi, E. Bonizzoni, A. Fantini, C. Resta, and G. Torelli, “A low-power low-voltage MOSFET-only voltage reference”, Proc. of IEEE International Symposium on Circuit and Systems (ISCAS), vol. 1, pp. 57-60, May 2004.
* F. Bedeschi, E. Bonizzoni, O. Khouri, C. Resta, and G. Torelli, “A fully symmetrical sense amplifier for non-volatile memories”, Proc. of IEEE International Symposium on Circuit and Systems (ISCAS), vol. 2, pp. 625-628, May 2004.
* E. Bonizzoni, A. Cabrini, O. Khouri, G. Torelli, “Algorithm for Automatic Design of Maximum-Efficiency Dickson Charge Pumps”, Proc. of IEEE European Conference on Circuits and Theory Design (ECCTD, vol. 2, pp.373-376, Sept. 2003.

 

 

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Laboratorio di Microsistemi Integrati - Via A. Ferrata 1, 27100, Pavia, Italy

Last Update: Thursday, August 21, 2008Tuesday, March 25, 2008